EXPERMENTAL ANALYSIS OF THE BOUNDARY SCAN AS DESIGN FOR TESTING TECHNIQUE | ||
| The International Conference on Electrical Engineering | ||
| Article 26, Volume 11, 11th International Conference on Electrical Engineering ICEENG 2018, April 2018, Pages 1-9 PDF (485.8 K) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/iceeng.2018.30151 | ||
| Authors | ||
| Hossam Ibrahim1; Magdy F. Ragaee2; Hassan Mostafa2 | ||
| 1Egyptian Armed Forces. | ||
| 2Dept. of Electronics and Electrical Communications Engineering Faculty of Engineering, Cairo University, Egypt. | ||
| Abstract | ||
| Boundary Scan testing is the IEEE Standard 1149.1 that overcomes many of the drawbacks of the other traditional test techniques. Boundary scan architecture enables us to go step in the direction of the portable testing systems. Designing testable circuits and interfacing it with the portable computer evaluate the design as a real time application. Therefore, IEEE-1149.1 boundary scan architecture is presented in this paper. A testing architecture of the boundary scan, designed for FPGA, is implemented and evaluated. Channel card of multiplexer is selected as a case study for this evaluation. | ||
| Keywords | ||
| DFT; ICT; Boundary scan; IEEE Standard 1149.1 | ||
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