Sayed, A., Hamed, H., Hasaneen, E. (2010). Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology. test, 7(7th International Conference on Electrical Engineering ICEENG 2010), 1-11. doi: 10.21608/iceeng.2010.33283
Alhassan. S. M. Sayed; Hesham F. A. Hamed; El-Sayed A.M. Hasaneen. "Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology". test, 7, 7th International Conference on Electrical Engineering ICEENG 2010, 2010, 1-11. doi: 10.21608/iceeng.2010.33283
Sayed, A., Hamed, H., Hasaneen, E. (2010). 'Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology', test, 7(7th International Conference on Electrical Engineering ICEENG 2010), pp. 1-11. doi: 10.21608/iceeng.2010.33283
Sayed, A., Hamed, H., Hasaneen, E. Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology. test, 2010; 7(7th International Conference on Electrical Engineering ICEENG 2010): 1-11. doi: 10.21608/iceeng.2010.33283

Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology

The International Conference on Electrical Engineering
Article 112, Volume 7, 7th International Conference on Electrical Engineering ICEENG 2010, May 2010, Pages 1-11    PDF (357.99 K)
Document Type: Original Article
DOI: 10.21608/iceeng.2010.33283
Authors
Alhassan. S. M. Sayed; Hesham F. A. Hamed; El-Sayed A.M. Hasaneen
Faculty of Engineering, Minia University, Minia, Egypt.
Abstract
Abstract:
In this paper, we present a fully integrated CMOS LNA (low noise amplifier) with input
matching LC ladder technique circuitry to cover the upper band of UWB from 3.1 to 10
GHz. Also, an improved technique of derivative superposition (DS) method is proposed
to improve the linearity by using both forward body bias technology, and currentreused.
The proposed LNA can operate at reduced supply voltage and power
consumption. This configuration provides better input matching, lower noise figure, and
more reverse isolation which is vital in LNA design. Complete analytical simulation of
the circuit results in frequency of 3.1 GHz to 10 GHz, with 2.44 dB NFMIN, 50Ω input
impedance, 13.5dB peak power gain (S21), high reverse isolation (S12) -50 dB, -15dB
input matching (S11) and -10dB output matching (S22), while dissipating as low power
as1.5mW low supply voltage of 0.6 V.
Keywords
CMOS; forward body bias; low noise amplifier (LNA); low voltage; Noise figure (NF); nonlinearity; third-order input intercept point (IIP3)
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