CMOS LOGIC FAMILIES FOR VLSI DESIGN | ||
| International Conference on Aerospace Sciences and Aviation Technology | ||
| Article 93, Volume 10, 10th International Conference On Aerospace Sciences & Aviation Technology, May 2003, Pages 827-838 PDF (1.52 M) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/asat.2001.59708 | ||
| Authors | ||
| SHEHATA K. A.1; TAHA A. K.2; ISMAIL M. A.3; MORSI K. M.2 | ||
| 1Asst. Prof., Faculty of Eng., Arab Academy for Science and Technology, Cairo, Egypt. | ||
| 2Egyptian Armed Forces. | ||
| 3Ph. D., Arabian Organization for Industrialization, Cairo, Egypt. | ||
| Abstract | ||
| In this paper, the investigation and evaluation of different stateof-the-art CMOS logic families, currently in use for VLSI design, are performed. These logic families are static CMOS logic, Pseudo-NMOS logic, Domino logic and Two-phase dynamic logic (TPDL). The main characteristics of these logic families, which are, power consumption, layout area and ease of implementation, are analyzed and compared. For the comparison among the different logic families, three basic logic gates are implemented using each of these logic families. The implemented gates are an Inverter, a 2-input NAND, and a 2-input NOR gates. The simulation is performed icing Tanner-Pro tools for different technologies starting from 1.6 urn to 0.25 um feature size at a power supply voltage (Vdd) of 5 volts. The technology parameters were extracted and measured from a fabrication lot by MOSIS SCN16 to SCNO25. | ||
| Keywords | ||
| VLSI design; Logic families; Static CMOS; Pseudo—NMOS; Domino logic; TPDL | ||
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