ANALYSIS AND DESIGN OF A MODIFIED GO-CFAR PROCESSOR. HARDWARE IMPLEMENTATION USING PLDs. | ||
| The International Conference on Electrical Engineering | ||
| Article 60, Volume 2, 2nd International Conference on Electrical Engineering ICEENG 1999, November 1999, Pages 609-620 PDF (2.51 M) | ||
| Document Type: Original Article | ||
| DOI: 10.21608/iceeng.1999.62574 | ||
| Authors | ||
| FATHY. M. ABDEL KADER1; ALI M. ABOU ZEID2; NABIL GIRGIS M.3 | ||
| 1Post graduate student, Main Workshops for Radar Equipment, Cairo, Egypt | ||
| 2Dr., Technical Research Center of the Armed Forces, Cairo, Egypt | ||
| 3Associate professor, Dpt. Of Radar and Guidance. MTC, Cairo, Egypt. | ||
| Abstract | ||
| Constant false alarm rate (CFAR) processors are useful for detecting radar targets in background noise for which all parameters of its statistical distribution are not known and may be non-stationary. The well known "Cell Averaging " (CA)-CFAR processor exhibits severe performance degradation in regions of abrupt change in the background clutter power. The " Greatest Of " (GO)-CFAR processor specially designed to control the false alarm rate during clutter power transition. A modification of the GO-CFAR processor is proposed Analysis for the selection of the sampling rate, window length, word length, and multiplication factor is introduced. The proposed design gives an improvement in detection capability and resolution of decision with a great reduction in hardware complexity. A further reduction in hardware complexity is obtained by using programmable logic devices (PLDs). These devices increase the effectively of using software in hardware which in turns, provide flexibility, modularity, expandability maintainability, and reduce size, cost, time and effort. | ||
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